This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction executing in the processor. To evaluate the proposed method, we use a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks and we consider the coverage and the detection latency for faults in the scheduler module of the microprocessor controller. Experimental results show that through this method, a large percentage of control logic faults can be detected with low latency during normal operation of the processor.
|Original language||English (US)|
|Number of pages||9|
|Journal||Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems|
|State||Published - 2008|
|Event||23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States|
Duration: Oct 1 2008 → Oct 3 2008
ASJC Scopus subject areas