TY - JOUR
T1 - Design and implementation of abacus switch
T2 - A scalable multicast ATM switch
AU - Chao, H. Jonathan
AU - Choe, Byeong Seog
AU - Park, Jin Soo
AU - Uzun, Necdet
N1 - Funding Information:
Manuscript received May 1, 1996; revised December 1, 1996. This work was supported by NSF Grant NCR-9216287, the Center of Advanced Technology for Telecommunications in New York State, the Electronics and Telecommunications Research Institute in Korea, and the Ministry of Information and Communication in Korea under Grant U96-186. This paper was presented in part at GLOBECOM’96, London, England, November 1996.
PY - 1997/6
Y1 - 1997/6
N2 - This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32 × 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz.
AB - This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32 × 32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz.
KW - Asynchronous transfer mode
KW - Contention resolution
KW - Large-scale switches
KW - Multicast switches
KW - Switching systems
UR - http://www.scopus.com/inward/record.url?scp=0031170338&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0031170338&partnerID=8YFLogxK
U2 - 10.1109/49.594845
DO - 10.1109/49.594845
M3 - Article
AN - SCOPUS:0031170338
VL - 15
SP - 830
EP - 843
JO - IEEE Journal on Selected Areas in Communications
JF - IEEE Journal on Selected Areas in Communications
SN - 0733-8716
IS - 5
ER -