Design and implementation of abacus switch: A scalable multicast ATM switch

This paper describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports and has buffers at input and output ports. A novel algorithm has been proposed to resolve output port contention while and achieves input buffers sharing, fairness among the input ports, and call splitting for multi-casting. The channel grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. A key component for building the Abacus switch called ATM Routing and Contention (ARC) chip has been implemented with CMOS 0.8-μm technology and tested to operate correctly at 240 Mbit/s. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is also presented.