TY - GEN
T1 - Design automation for hybrid CMOS-nanoelectronics crossbars
AU - Kim, Kyosun
AU - Karri, Ramesh
AU - Orailoglu, Alex
PY - 2007
Y1 - 2007
N2 - We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL [5]. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.
AB - We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL [5]. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.
KW - Automatic Layout Design
KW - MOL FPGA
UR - http://www.scopus.com/inward/record.url?scp=50849120393&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50849120393&partnerID=8YFLogxK
U2 - 10.1109/NANOARCH.2007.4400854
DO - 10.1109/NANOARCH.2007.4400854
M3 - Conference contribution
AN - SCOPUS:50849120393
SN - 9781424417919
T3 - 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
SP - 27
EP - 32
BT - 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
PB - IEEE Computer Society
T2 - 2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH
Y2 - 21 October 2007 through 22 October 2007
ER -