Design for testability support for launch and capture power reduction in launch-off-shift and launch-off-capture testing

Keyphrases

• Design for Testability 100%
• Capture Power 100%
• Launch-off-capture 100%
• Launch Power 100%
• At-speed Test 50%
• Pattern Count 50%
• Activity Limitations 25%
• Test Pattern 25%
• Low Power 25%
• Highly Effective 25%
• Proposed Design 25%
• Pattern Generation 25%
• Partitioning Strategy 25%
• Test Cost 25%
• VLSI Circuits 25%
• One-at-a-time 25%
• Multiple Delays 25%
• Test Quality 25%
• Compact Test 25%
• Launch Operations 25%
• Design Flow 25%
• Yield Loss 25%
• Peak Power Constraint 25%
• Switching Activity 25%
• Pattern Quality 25%
• At-speed 25%
• Low Switching Activity 25%
• Design Partitioning 25%
• Count Inflation 25%
• Design Region 25%
• Quality Screening 25%
• Delay Faults 25%
• Targeting Performance 25%
• Capture Operation 25%

Computer Science

• Switching Activity 100%
• Power Constraint 50%
• Related Performance 50%
• Partitioning Approach 50%
• Capture Operation 50%

Engineering

• Testability 100%
• Switching Activity 50%
• VLSI Circuits 25%
• Design Flow 25%
• Peak Power Constraint 25%