TY - GEN
T1 - Design Obfuscation versus Test
AU - Farahmandi, Farimah
AU - Sinanoglu, Ozgur
AU - Blanton, Ronald
AU - Pagliarini, Samuel
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rd party IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction-here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own.
AB - The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rd party IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction-here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own.
KW - Test
KW - automatic test pattern generation
KW - high level synthesis
KW - integrated circuit design
KW - logic locking
KW - logic obfuscation
UR - http://www.scopus.com/inward/record.url?scp=85089159437&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85089159437&partnerID=8YFLogxK
U2 - 10.1109/ETS48528.2020.9131590
DO - 10.1109/ETS48528.2020.9131590
M3 - Conference contribution
AN - SCOPUS:85089159437
T3 - Proceedings of the European Test Workshop
BT - Proceedings - 2020 IEEE European Test Symposium, ETS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE European Test Symposium, ETS 2020
Y2 - 25 May 2020 through 29 May 2020
ER -