Design Obfuscation versus Test

Farimah Farahmandi, Ozgur Sinanoglu, Ronald Blanton, Samuel Pagliarini

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rd party IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction-here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own.

Original languageEnglish (US)
Title of host publicationProceedings - 2020 IEEE European Test Symposium, ETS 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728143125
DOIs
StatePublished - May 2020
Event2020 IEEE European Test Symposium, ETS 2020 - Tallinn, Estonia
Duration: May 25 2020May 29 2020

Publication series

NameProceedings of the European Test Workshop
Volume2020-May
ISSN (Print)1530-1877
ISSN (Electronic)1558-1780

Conference

Conference2020 IEEE European Test Symposium, ETS 2020
CountryEstonia
CityTallinn
Period5/25/205/29/20

Keywords

  • automatic test pattern generation
  • high level synthesis
  • integrated circuit design
  • logic locking
  • logic obfuscation
  • Test

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Software

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  • Cite this

    Farahmandi, F., Sinanoglu, O., Blanton, R., & Pagliarini, S. (2020). Design Obfuscation versus Test. In Proceedings - 2020 IEEE European Test Symposium, ETS 2020 [9131590] (Proceedings of the European Test Workshop; Vol. 2020-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ETS48528.2020.9131590