Design of a bufferless photonic CIos network-on-chip architecture

Yu Hsiang Kao, H. Jonathan Chao

Research output: Contribution to journalArticlepeer-review


On-chip photonic waveguides have been proposed as a feasible replacement for the long interconnects that cause speed and power bottlenecks. Along with recent advancements in nanophotonic technologies, we believe that combining on-chip waveguides with high-radix Network on Chip (NoC) topologies is a promising way to improve NoC performance. In this paper, we propose the BufferLess phOtonic ClOs Network (BLOCON) to exploit silicon photonics. We propose a scheduling algorithm named Sustained and Informed Dual Round-Robin Matching (SIDRRM) to solve the output contention problem, a path allocation scheme named Distributed and Informed Path Allocation (DIPA) to solve the Clos network routing problem, and a methodology to achieve an optimal off-chip laser-power budget. In the simulation results, we show that with SIDRRM and DIPA, BLOCON improves the delay and on-chip power performance of the compared electrical and photonic NoC architectures over synthetic traffic patterns and SPLASH-2 traces.

Original languageEnglish (US)
Article number6331481
Pages (from-to)764-776
Number of pages13
JournalIEEE Transactions on Computers
Issue number3
StatePublished - Mar 2014


  • Clos network
  • Network-on-chip
  • bufferless NoC
  • silicon photonics

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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