@inproceedings{0bc1cedc3cf64d9db4cf6288027a782b,
title = "Design of high-radix Clos Network-on-Chip",
abstract = "Many high-radix Network-on-Chip (NOC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe Clos Network-on-Chip (CNOC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose (1) a high-radix router architecture with Virtual Output Queue (VOQ) buffer structure and Packet Mode Dual Round-Robin Matching (PDRRM) scheduling algorithm to achieve high speed and high throughput in CNOC, (2) a heuristic floor-planning algorithm to minimize the power consumption caused by the long wires. Experimental results show that the throughput of a 64-node 3-stage CNOC under uniform traffic increases from 62% to 78% by replacing the baseline routers with PDRRM VOQ routers. We also compared CNOC with other NOC topologies, and found that using the new design techniques, CNOC has the highest throughput, lowest zero-load latency, and best power efficiency.",
keywords = "Chip multiprocessor, Clos network, High radix NOC, Network on Chip",
author = "Kao, {Yu Hsiang} and Najla Alfaraj and Ming Yang and Chao, {H. Jonathan}",
year = "2010",
doi = "10.1109/NOCS.2010.27",
language = "English (US)",
isbn = "9780769540535",
series = "NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip",
pages = "181--188",
booktitle = "NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip",
note = "4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010 ; Conference date: 03-05-2010 Through 06-05-2010",
}