TY - GEN
T1 - Design Space Exploration of Modular Multipliers for ASIC FHE accelerators
AU - Soni, Deepraj
AU - Nabeel, Mohammed
AU - Gamil, Homer
AU - Mazonka, Oleg
AU - Reagen, Brandon
AU - Karri, Ramesh
AU - Maniatakos, Michail
N1 - Funding Information:
VIII. RESOURCES All the design files, synthesis scripts, and power analysis scripts are at: https://github.com/momalab/modular-multipliers IX. ACKNOWLEDGEMENT This work has been partially funded by the Defense Advanced Research Projects Agency (DARPA) under the Data Protection in Virtual Environments (DPRIVE) program, contract no. HR0011-21-9-0003.
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Fully homomorphic encryption (FHE) promises data protection by computation on encrypted data, but demands resource-intensive computation. The most fundamental resource of FHE is modular multiplier, which needs to be evaluated for efficient implementation. In this work, we develop and evaluate ASIC implementations of the modular multiplier at the block-level and at the system-level. We study the efficiency of the multipliers in terms of performance-for-area and performance-for-power. Since these ASICs are used in FHE, we explore these multipliers within this system-level context with on-chip memory and interconnect limits. We explore ASIC implementations of modular multiplications using a state-of-the-art 22nm technology node with constant operand throughput to ensure a fair comparison. The study yields key insights about the performance-for-area efficiency and power efficiency of bit-serial and bit-parallel designs: Bit-parallel designs are more efficient than their bitserial counterparts. Montgomery multipliers with constrained modulus are the most power-efficient and area-efficient design. Iterative Montgomery multipliers incur minimum peak power for a polynomial multiplication, making them suitable for low-power voltage sources.
AB - Fully homomorphic encryption (FHE) promises data protection by computation on encrypted data, but demands resource-intensive computation. The most fundamental resource of FHE is modular multiplier, which needs to be evaluated for efficient implementation. In this work, we develop and evaluate ASIC implementations of the modular multiplier at the block-level and at the system-level. We study the efficiency of the multipliers in terms of performance-for-area and performance-for-power. Since these ASICs are used in FHE, we explore these multipliers within this system-level context with on-chip memory and interconnect limits. We explore ASIC implementations of modular multiplications using a state-of-the-art 22nm technology node with constant operand throughput to ensure a fair comparison. The study yields key insights about the performance-for-area efficiency and power efficiency of bit-serial and bit-parallel designs: Bit-parallel designs are more efficient than their bitserial counterparts. Montgomery multipliers with constrained modulus are the most power-efficient and area-efficient design. Iterative Montgomery multipliers incur minimum peak power for a polynomial multiplication, making them suitable for low-power voltage sources.
KW - ASIC acceleration
KW - Barrett Reduction
KW - Design Space Exploration
KW - Interleaved Multiplier
KW - Lattice-based Cryptography
KW - Modular Multiplier
KW - Montgomery Reduction
KW - Number Theoretic Transform
KW - Polynomial Multiplication
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U2 - 10.1109/ISQED57927.2023.10129292
DO - 10.1109/ISQED57927.2023.10129292
M3 - Conference contribution
AN - SCOPUS:85161605360
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
BT - Proceedings of the 24th International Symposium on Quality Electronic Design, ISQED 2023
PB - IEEE Computer Society
T2 - 24th International Symposium on Quality Electronic Design, ISQED 2023
Y2 - 5 April 2023 through 7 April 2023
ER -