Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology

Given their non-invasiveness and demonstrated effectiveness, power analysis attacks (PAAs) are concerning and to be accounted for in modern circuit design. That is especially relevant for technology-dependent verification of PAA countermeasure implementations. Prior art proposed various countermeasures against PAAs, including masking and hiding, voltage switching, noise injection, etc. Aside from the proven working principles of such countermeasures, it is important to understand that their effectiveness is primarily technology- and implementation-dependent. Hence, before deployment, especially for integrated circuits, such countermeasures require accurate circuit-level studies. This work investigates an industrial-grade 14 nm fin field-effect transistor (FinFET) technology at design-time in the context of PAAs. We leverage device-level measurement data from Intel high-volume manufacturing processes, build up accordingly well-characterized standard-cell libraries, and utilize a commercial-grade computer-aided design (CAD) flow for PAA evaluation at design-time. Our study is focused on (1) the effectiveness of voltage switching as a countermeasure, (2) the advanced encryption standard (AES) cipher as a representative circuit, and (3) the correlation power analysis (CPA) as an attack framework. We show that, to improve the resilience against the CPA attack in particular and to lower information leakage in general, specific voltage configurations are more promising than others for the 14 nm FinFET technology.