@inproceedings{3c10d14203f849eb948c84bd566ba8ca,
title = "Designing ML-resilient locking at register-transfer level",
abstract = "Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are applied on the gate-level netlist after logic synthesis, they have no semantic knowledge of the design function. Data-driven, machine-learning (ML) attacks can uncover the design flaws within gate-level locking. Recent proposals on register-transfer level (RTL) locking have access to semantic hardware information. We investigate the resilience of ASSURE, a state-of-the-art RTL locking method, against ML attacks. We used the lessons learned to derive two ML-resilient RTL locking schemes built to reinforce ASSURE locking. We developed ML-driven security metrics to evaluate the schemes against an RTL adaptation of the state-of-the-art, ML-based SnapShot attack.",
keywords = "IP protection, RTL, deobfuscation, logic locking, machine learning",
author = "Dominik Sisejkovic and Luca Collini and Benjamin Tan and Christian Pilato and Ramesh Karri and Rainer Leupers",
note = "Publisher Copyright: {\textcopyright} 2022 ACM.; 59th ACM/IEEE Design Automation Conference, DAC 2022 ; Conference date: 10-07-2022 Through 14-07-2022",
year = "2022",
month = jul,
day = "10",
doi = "10.1145/3489517.3530541",
language = "English (US)",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "769--774",
booktitle = "Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022",
}