DfST: Design for secure testability

Samah Mohamed Saeed; Ozgur Sinanoglu

doi:10.1109/TEST.2014.7035365

DfST: Design for secure testability

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC.We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.

Original language	English (US)
Title of host publication	Proceedings - 2014 IEEE International Test Conference, ITC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479947225
DOIs	https://doi.org/10.1109/TEST.2014.7035365
State	Published - Feb 6 2015
Event	45th IEEE International Test Conference, ITC 2014 - Seattle, United States Duration: Oct 21 2014 → Oct 23 2014

Publication series

Name	Proceedings - International Test Conference
Volume	2015-February
ISSN (Print)	1089-3539

Other

Other	45th IEEE International Test Conference, ITC 2014
Country/Territory	United States
City	Seattle
Period	10/21/14 → 10/23/14

ASJC Scopus subject areas

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.2014.7035365

Cite this

Saeed, SM & Sinanoglu, O 2015, DfST: Design for secure testability. in Proceedings - 2014 IEEE International Test Conference, ITC 2014., 7035365, Proceedings - International Test Conference, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., 45th IEEE International Test Conference, ITC 2014, Seattle, United States, 10/21/14. https://doi.org/10.1109/TEST.2014.7035365

@inproceedings{a0db4a7b29934bf7b66cae3011867284,

title = "DfST: Design for secure testability",

abstract = "While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC.We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.",

author = "Saeed, {Samah Mohamed} and Ozgur Sinanoglu",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 45th IEEE International Test Conference, ITC 2014 ; Conference date: 21-10-2014 Through 23-10-2014",

year = "2015",

month = feb,

day = "6",

doi = "10.1109/TEST.2014.7035365",

language = "English (US)",

series = "Proceedings - International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - 2014 IEEE International Test Conference, ITC 2014",

}

TY - GEN

T1 - DfST

T2 - 45th IEEE International Test Conference, ITC 2014

AU - Saeed, Samah Mohamed

AU - Sinanoglu, Ozgur

PY - 2015/2/6

Y1 - 2015/2/6

N2 - While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC.We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.

AB - While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC.We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.

UR - http://www.scopus.com/inward/record.url?scp=84954289512&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84954289512&partnerID=8YFLogxK

U2 - 10.1109/TEST.2014.7035365

DO - 10.1109/TEST.2014.7035365

M3 - Conference contribution

AN - SCOPUS:84954289512

T3 - Proceedings - International Test Conference

BT - Proceedings - 2014 IEEE International Test Conference, ITC 2014

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 21 October 2014 through 23 October 2014

ER -

DfST: Design for secure testability

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this