DfST: Design for secure testability

Samah Mohamed Saeed, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

While manufacturing test necessitates deep access into the Integrated Circuit (IC) to enhance its testability, this can inadvertently threaten the security of the IC in security-critical applications. Although black-box testing ensures security, it fails to deliver high-quality test. Therefore, our goal is to come up with DFT techniques that deliver testability without compromising the security of the IC.We propose various DFT techniques that tackle the testing challenges, such as test time, test data volume, and test power. Furthermore, we propose different scan attacks, which circumvent the security of the IC in the presence of advanced DFT techniques. We identify the limitations of our proposed scan attacks to develop countermeasures that can thwart these attacks.

Original languageEnglish (US)
Title of host publicationProceedings - 2014 IEEE International Test Conference, ITC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479947225
DOIs
StatePublished - Feb 6 2015
Event45th IEEE International Test Conference, ITC 2014 - Seattle, United States
Duration: Oct 21 2014Oct 23 2014

Publication series

NameProceedings - International Test Conference
Volume2015-February
ISSN (Print)1089-3539

Other

Other45th IEEE International Test Conference, ITC 2014
CountryUnited States
CitySeattle
Period10/21/1410/23/14

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Saeed, S. M., & Sinanoglu, O. (2015). DfST: Design for secure testability. In Proceedings - 2014 IEEE International Test Conference, ITC 2014 [7035365] (Proceedings - International Test Conference; Vol. 2015-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2014.7035365