Do not trust, verify: A verifiable hardware accelerator for matrix multiplication

Maria I. Mera Collantes; Siddharth Garg

doi:10.1109/LES.2019.2953485

Do not trust, verify: A verifiable hardware accelerator for matrix multiplication

Maria I. Mera Collantes, Siddharth Garg

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling 11\times-69\times speed-ups compared with software execution.

Original language	English (US)
Article number	8901198
Pages (from-to)	70-73
Number of pages	4
Journal	IEEE Embedded Systems Letters
Volume	12
Issue number	3
DOIs	https://doi.org/10.1109/LES.2019.2953485
State	Published - Sep 2020

Keywords

Embedded systems security
field programmable gate array (FPGA)
secure hardware

ASJC Scopus subject areas

Control and Systems Engineering
General Computer Science

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10.1109/LES.2019.2953485

Cite this

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abstract = "In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling 11\times-69\times speed-ups compared with software execution.",

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Do not trust, verify: A verifiable hardware accelerator for matrix multiplication

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Keywords

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