TY - JOUR
T1 - Do not trust, verify
T2 - A verifiable hardware accelerator for matrix multiplication
AU - Mera Collantes, Maria I.
AU - Garg, Siddharth
N1 - Funding Information:
Manuscript received June 19, 2019; accepted September 17, 2019. Date of publication November 13, 2019; date of current version August 27, 2020. This work was supported in part by the National Science Foundation (NSF) under Award 1565396, and in part by NSF CAREER under Award 1553419. This manuscript was recommended for publication by Y. Xie. (Corresponding author: Maria I. Mera Collantes.) The authors are with the Department of Electrical and Computer Engineering, New York University, Brooklyn, NY 11201 USA (e-mail: mimera@nyu.edu; sg175@nyu.edu). Digital Object Identifier 10.1109/LES.2019.2953485 Fig. 1. Overview of VeritAcc solution. Shaded region denotes trusted hardware resources; the rest is untrusted. Stars indicate possible HT insertion locations.
Publisher Copyright:
© 2009-2012 IEEE.
PY - 2020/9
Y1 - 2020/9
N2 - In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling 11\times-69\times speed-ups compared with software execution.
AB - In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling 11\times-69\times speed-ups compared with software execution.
KW - Embedded systems security
KW - field programmable gate array (FPGA)
KW - secure hardware
UR - http://www.scopus.com/inward/record.url?scp=85081301234&partnerID=8YFLogxK
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U2 - 10.1109/LES.2019.2953485
DO - 10.1109/LES.2019.2953485
M3 - Article
AN - SCOPUS:85081301234
SN - 1943-0663
VL - 12
SP - 70
EP - 73
JO - IEEE Embedded Systems Letters
JF - IEEE Embedded Systems Letters
IS - 3
M1 - 8901198
ER -