Do not trust, verify: A verifiable hardware accelerator for matrix multiplication

Maria I. Mera Collantes, Siddharth Garg

Research output: Contribution to journalArticlepeer-review

Abstract

In this letter, we propose VeritAcc, a novel application that enables secure integration of an untrusted third-party matrix multiplication (MM) hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of VeritAcc. We show that an field programmable gate array (FPGA) prototype of VeritAcc introduces less than 6.25% digital signal processing (DSP) area overhead compared to a baseline untrusted MM accelerator while enabling 11\times-69\times speed-ups compared with software execution.

Original languageEnglish (US)
Article number8901198
Pages (from-to)70-73
Number of pages4
JournalIEEE Embedded Systems Letters
Volume12
Issue number3
DOIs
StatePublished - Sep 2020

Keywords

  • Embedded systems security
  • field programmable gate array (FPGA)
  • secure hardware

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)

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