Don’t Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication

Maria I.Mera Collantes, Siddharth Garg

Research output: Contribution to journalArticle

Abstract

In this paper, we propose , a novel application that enables secure integration of an untrusted third-party matrix multiplication hardware accelerator in a system-on-chip containing a trusted general purpose processor. Our solution builds upon the theory of interactive proof (IP) protocols to enable run-time verification of each computation executed on the untrusted accelerator and formally guarantees that any incorrect results are detected with high probability. Our novel optimizations in hardware implementation reduces area and performance overhead of . We show that an FPGA prototype of introduces less than 6.25% DSP area overhead compared to a baseline untrusted matrix multiplication accelerator while enabling 11x-69x speed-ups compared to software execution.

Original languageEnglish (US)
JournalIEEE Embedded Systems Letters
DOIs
StateAccepted/In press - 2019

Keywords

  • FPGA.
  • Hardware
  • IP networks
  • Optimization
  • Protocols
  • System-on-chip
  • Trojan horses
  • embedded systems security
  • secure hardware

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)

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