TY - GEN
T1 - DRMap
T2 - 57th ACM/IEEE Design Automation Conference, DAC 2020
AU - Wicaksana Putra, Rachmad Vidya
AU - Abdullah Hanif, Muhammad
AU - Shafique, Muhammad
N1 - Funding Information:
Authors acknowledge the scholarship granted by Indonesia Endowment Fund for Education (IEFE/LPDP), Ministry of Finance, Republic of Indonesia.
Publisher Copyright:
© 2020 IEEE.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2020/7
Y1 - 2020/7
N2 - Many convolutional neural network (CNN) accelerators face performance- and energy-efficiency challenges which are crucial for embedded implementations, due to high DRAM access latency and energy. Recently, some DRAM architectures have been proposed to exploit subarray-level parallelism for decreasing the access latency. Towards this, we present a design space exploration methodology to study the latency and energy of different mapping policies on different DRAM architectures, and identify the pareto-optimal design choices. The results show that the energy-efficient DRAM accesses can be achieved by a mapping policy that orderly prioritizes to maximize the row buffer hits, bank- and subarray-level parallelism.
AB - Many convolutional neural network (CNN) accelerators face performance- and energy-efficiency challenges which are crucial for embedded implementations, due to high DRAM access latency and energy. Recently, some DRAM architectures have been proposed to exploit subarray-level parallelism for decreasing the access latency. Towards this, we present a design space exploration methodology to study the latency and energy of different mapping policies on different DRAM architectures, and identify the pareto-optimal design choices. The results show that the energy-efficient DRAM accesses can be achieved by a mapping policy that orderly prioritizes to maximize the row buffer hits, bank- and subarray-level parallelism.
KW - CNN accelerators
KW - CNNs
KW - Convolutional neural networks
KW - DRAM architectures
KW - DRAM mapping
KW - Subarray-level parallelism
UR - http://www.scopus.com/inward/record.url?scp=85093956996&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85093956996&partnerID=8YFLogxK
U2 - 10.1109/DAC18072.2020.9218672
DO - 10.1109/DAC18072.2020.9218672
M3 - Conference contribution
AN - SCOPUS:85093956996
T3 - Proceedings - Design Automation Conference
BT - 2020 57th ACM/IEEE Design Automation Conference, DAC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 20 July 2020 through 24 July 2020
ER -