TY - GEN
T1 - DRVS
T2 - 20th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2015
AU - Salehi, Mohammad
AU - Tavana, Mohammad Khavari
AU - Rehman, Semeen
AU - Kriebel, Florian
AU - Shafique, Muhammad
AU - Ejlali, Alireza
AU - Henkel, Jörg
N1 - Publisher Copyright:
© 2015 IEEE.
Copyright:
Copyright 2016 Elsevier B.V., All rights reserved.
PY - 2015/9/21
Y1 - 2015/9/21
N2 - Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling (DRVS) considering process variations in hardware, and diversities in software vulnerability and execution time properties. Experiments show that DRVS system provides significant reliability improvements while providing up to 60% reduced power consumption compared to state-of-the-art techniques.
AB - Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling (DRVS) considering process variations in hardware, and diversities in software vulnerability and execution time properties. Experiments show that DRVS system provides significant reliability improvements while providing up to 60% reduced power consumption compared to state-of-the-art techniques.
KW - Power demand
KW - Redundancy
KW - Software
KW - Software reliability
KW - Timing
KW - Tunneling magnetoresistance
UR - http://www.scopus.com/inward/record.url?scp=84958523582&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84958523582&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2015.7273518
DO - 10.1109/ISLPED.2015.7273518
M3 - Conference contribution
AN - SCOPUS:84958523582
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 225
EP - 230
BT - Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 July 2015 through 24 July 2015
ER -