Dynamic test data transformations for average and peak power reductions

Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu

Research output: Contribution to journalConference articlepeer-review

Abstract

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths with no performance degradation. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.

Original languageEnglish (US)
Article number1029647
Pages (from-to)113-118
Number of pages6
JournalProceedings of the European Test Workshop
Volume2002-January
Issue numberJanuary
DOIs
StatePublished - 2002
Event7th IEEE European Test Workshop, ETW 2002 - Corfu, Greece
Duration: May 26 2002May 29 2002

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Software

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