TY - GEN
T1 - E-pipeline
T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
AU - Zhang, Xi
AU - Javaid, Haris
AU - Shafique, Muhammad
AU - Peddersen, Jorgen
AU - Henkel, Jorg
AU - Parameswaran, Sri
N1 - Publisher Copyright:
© 2015 EDAA.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2015/4/22
Y1 - 2015/4/22
N2 - On-chip many-core systems are expected to be in common use in the future. A set of homogeneous processors in a many-core system can be used to implement multiple pipelines which execute simultaneously. Pipelines of processors use varying numbers of cores when their workloads vary at run time. In this paper, we show how such a system executing multiple pipelines with varying workloads can be implemented. We further show how the system can switch cores within a pipeline (intra-elasticity) and between pipelines (inter-elasticity). The method is named E-pipeline, and is implemented and evaluated in a commercial tool suite. Compared to reference design methods with clock gating, E-pipeline achieves the same power savings, maintains the throughput to meet throughput constraints and reduces core usage by an average of 37.7%. The adaptation overhead for switching cores is approximately 2μs.
AB - On-chip many-core systems are expected to be in common use in the future. A set of homogeneous processors in a many-core system can be used to implement multiple pipelines which execute simultaneously. Pipelines of processors use varying numbers of cores when their workloads vary at run time. In this paper, we show how such a system executing multiple pipelines with varying workloads can be implemented. We further show how the system can switch cores within a pipeline (intra-elasticity) and between pipelines (inter-elasticity). The method is named E-pipeline, and is implemented and evaluated in a commercial tool suite. Compared to reference design methods with clock gating, E-pipeline achieves the same power savings, maintains the throughput to meet throughput constraints and reduces core usage by an average of 37.7%. The adaptation overhead for switching cores is approximately 2μs.
UR - http://www.scopus.com/inward/record.url?scp=84945911394&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84945911394&partnerID=8YFLogxK
U2 - 10.7873/date.2015.0203
DO - 10.7873/date.2015.0203
M3 - Conference contribution
AN - SCOPUS:84945911394
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 363
EP - 368
BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 March 2015 through 13 March 2015
ER -