E-pipeline: Elastic hardware/software pipelines on a many-core fabric

Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jorg Henkel, Sri Parameswaran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

On-chip many-core systems are expected to be in common use in the future. A set of homogeneous processors in a many-core system can be used to implement multiple pipelines which execute simultaneously. Pipelines of processors use varying numbers of cores when their workloads vary at run time. In this paper, we show how such a system executing multiple pipelines with varying workloads can be implemented. We further show how the system can switch cores within a pipeline (intra-elasticity) and between pipelines (inter-elasticity). The method is named E-pipeline, and is implemented and evaluated in a commercial tool suite. Compared to reference design methods with clock gating, E-pipeline achieves the same power savings, maintains the throughput to meet throughput constraints and reduces core usage by an average of 37.7%. The adaptation overhead for switching cores is approximately 2μs.

Original languageEnglish (US)
Title of host publicationProceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages363-368
Number of pages6
ISBN (Electronic)9783981537048
DOIs
StatePublished - Apr 22 2015
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: Mar 9 2015Mar 13 2015

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume2015-April
ISSN (Print)1530-1591

Other

Other2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period3/9/153/13/15

ASJC Scopus subject areas

  • Engineering(all)

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