TY - GEN
T1 - Efficient Hardware Implementation of PQC Primitives and PQC algorithms Using High-Level Synthesis
AU - Soni, Deepraj
AU - Karri, Ramesh
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/7
Y1 - 2021/7
N2 - Efficient and quantum-resistant Post-Quantum Cryptographic (PQC) algorithms need to be built before development of large-scale quantum, which will break RSA and Elliptic Curve cryptography based existing public key infrastructure. Cryptographers are developing quantum-resistant PQC algorithms, which consist of PQC primitives. These primitives act as a basic building blocks that play a vital role in security and resource utilization. Hence, efficient and precise implementation of PQC primitives is crucial for stable PQC algorithms. This paper implements and optimizes PQC primitives using High-level synthesis. High-level synthesis produces area-optimized and speed-optimized solutions for the primitives. These solutions create efficient and constant-time PQC designs that keep the hardware secure against timing side-channel attack.
AB - Efficient and quantum-resistant Post-Quantum Cryptographic (PQC) algorithms need to be built before development of large-scale quantum, which will break RSA and Elliptic Curve cryptography based existing public key infrastructure. Cryptographers are developing quantum-resistant PQC algorithms, which consist of PQC primitives. These primitives act as a basic building blocks that play a vital role in security and resource utilization. Hence, efficient and precise implementation of PQC primitives is crucial for stable PQC algorithms. This paper implements and optimizes PQC primitives using High-level synthesis. High-level synthesis produces area-optimized and speed-optimized solutions for the primitives. These solutions create efficient and constant-time PQC designs that keep the hardware secure against timing side-channel attack.
KW - Dilithium Hardware Design
KW - High Level Synthesis
KW - Kyber Hardware Design
KW - PQC Primitives
KW - Post-Quantum Cryptography
UR - http://www.scopus.com/inward/record.url?scp=85114965189&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85114965189&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI51109.2021.00061
DO - 10.1109/ISVLSI51109.2021.00061
M3 - Conference contribution
AN - SCOPUS:85114965189
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 296
EP - 301
BT - Proceedings - 2021 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
PB - IEEE Computer Society
T2 - 20th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021
Y2 - 7 July 2021 through 9 July 2021
ER -