Efficient processor arrays for the implementation of the generalised predictive-control algorithm

Processor-array architectures for the efficient implementation of the generalised predictive-control (GPC) algorithm are introduced, each exhibiting different area/time performance, processor utilisation and degree of programmability. The special features that the partial algorithms of GPC exhibit have been exploited, to derive efficient architectures of low complexity. A remarkable reduction of the execution time required for a complete cycle of the algorithm is achieved, compared with the long delay of executing the algorithm on a single processor.