TY - GEN
T1 - Eliminating performance penalty of scan
AU - Sinanoglu, Ozgur
PY - 2012
Y1 - 2012
N2 - Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.
AB - Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.
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U2 - 10.1109/VLSID.2012.95
DO - 10.1109/VLSID.2012.95
M3 - Conference contribution
AN - SCOPUS:84859886408
SN - 9780769546384
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 346
EP - 351
BT - Proceedings - 25th International Conference on VLSI Design, VLSI Design 2012 - Held Jointly with 11th International Conference on Embedded Systems
PB - IEEE Computer Society
T2 - 25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems
Y2 - 7 January 2012 through 11 January 2012
ER -