While advancements in chip manufacturing technology has accelerated the growth of embedded systems, it has revealed serious reliability and robustness challenges at various abstraction levels that threaten the applicability of scaled technologies [2, 3]. These reliability threats arise from multiple sources, and may result in faults in the hardware. Furthermore, these faults in the hardware may have catastrophic effects on the correctness of software execution [9, 11, 14]. This is particularly the case for real-time and timing-critical embedded systems involved in safety-, and mission-critical systems . This occurs because traditional software abstraction layers make the fundamental assumption that the underlying hardware platform is error-free, and completely reliable. This is, however, no longer the case. In order to mitigate various reliability threats, besides hardware-level techniques, it is critical to develop and design resiliency at various layers of the embedded software stack [2, 3].