Enabling timing error resilience for low-power systolic-array based deep learning accelerators

Jeff Zhang, Zahra Ghodsi, Siddharth Garg, Kartheek Rangineni

Research output: Contribution to journalArticlepeer-review

Abstract

Hardware-accelerated learning and inference algorithms are quite popular in edge devices where predictable timing behavior and minimal energy consumption are required, while maintaining robustness to timing errors. To achieve this, dynamic voltage scaling techniques have been utilized in several accelerators. Therefore, this article presents Thundervolt, a framework allowing adaptive aggressive voltage underscaling while maintaining the robustness (reliability, predictability, performance) of such accelerators. - Theocharis Theocharides, University of Cyprus - Muhammad Shafique, Technische Universitat Wien.

Original languageEnglish (US)
Article number8868188
Pages (from-to)93-102
Number of pages10
JournalIEEE Design and Test
Volume37
Issue number2
DOIs
StatePublished - Apr 2020

Keywords

  • Deep Neural Network
  • Energy Efficiency
  • Hardware Accelerator
  • Systolic Arrays
  • Timing Error
  • Timing Speculation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Enabling timing error resilience for low-power systolic-array based deep learning accelerators'. Together they form a unique fingerprint.

Cite this