Enabling timing error resilience for low-power systolic-array based deep learning accelerators

Jeff Zhang; Zahra Ghodsi; Siddharth Garg; Kartheek Rangineni

doi:10.1109/MDAT.2019.2947271

Enabling timing error resilience for low-power systolic-array based deep learning accelerators

Jeff Zhang, Zahra Ghodsi, Siddharth Garg, Kartheek Rangineni

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Hardware-accelerated learning and inference algorithms are quite popular in edge devices where predictable timing behavior and minimal energy consumption are required, while maintaining robustness to timing errors. To achieve this, dynamic voltage scaling techniques have been utilized in several accelerators. Therefore, this article presents Thundervolt, a framework allowing adaptive aggressive voltage underscaling while maintaining the robustness (reliability, predictability, performance) of such accelerators. - Theocharis Theocharides, University of Cyprus - Muhammad Shafique, Technische Universitat Wien.

Original language	English (US)
Article number	8868188
Pages (from-to)	93-102
Number of pages	10
Journal	IEEE Design and Test
Volume	37
Issue number	2
DOIs	https://doi.org/10.1109/MDAT.2019.2947271
State	Published - Apr 2020

Keywords

Deep Neural Network
Energy Efficiency
Hardware Accelerator
Systolic Arrays
Timing Error
Timing Speculation

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MDAT.2019.2947271

Cite this

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title = "Enabling timing error resilience for low-power systolic-array based deep learning accelerators",

abstract = "Hardware-accelerated learning and inference algorithms are quite popular in edge devices where predictable timing behavior and minimal energy consumption are required, while maintaining robustness to timing errors. To achieve this, dynamic voltage scaling techniques have been utilized in several accelerators. Therefore, this article presents Thundervolt, a framework allowing adaptive aggressive voltage underscaling while maintaining the robustness (reliability, predictability, performance) of such accelerators. - Theocharis Theocharides, University of Cyprus - Muhammad Shafique, Technische Universitat Wien.",

keywords = "Deep Neural Network, Energy Efficiency, Hardware Accelerator, Systolic Arrays, Timing Error, Timing Speculation",

author = "Jeff Zhang and Zahra Ghodsi and Siddharth Garg and Kartheek Rangineni",

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N2 - Hardware-accelerated learning and inference algorithms are quite popular in edge devices where predictable timing behavior and minimal energy consumption are required, while maintaining robustness to timing errors. To achieve this, dynamic voltage scaling techniques have been utilized in several accelerators. Therefore, this article presents Thundervolt, a framework allowing adaptive aggressive voltage underscaling while maintaining the robustness (reliability, predictability, performance) of such accelerators. - Theocharis Theocharides, University of Cyprus - Muhammad Shafique, Technische Universitat Wien.

AB - Hardware-accelerated learning and inference algorithms are quite popular in edge devices where predictable timing behavior and minimal energy consumption are required, while maintaining robustness to timing errors. To achieve this, dynamic voltage scaling techniques have been utilized in several accelerators. Therefore, this article presents Thundervolt, a framework allowing adaptive aggressive voltage underscaling while maintaining the robustness (reliability, predictability, performance) of such accelerators. - Theocharis Theocharides, University of Cyprus - Muhammad Shafique, Technische Universitat Wien.

KW - Deep Neural Network

KW - Energy Efficiency

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KW - Systolic Arrays

KW - Timing Error

KW - Timing Speculation

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Enabling timing error resilience for low-power systolic-array based deep learning accelerators

Abstract

Keywords

ASJC Scopus subject areas

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