Engineering crossbar based emerging memory technologies

Sachhidh Kannan; Jeyavijayan Rajendran; Ramesh Karri; Ozgur Sinanoglu

doi:10.1109/ICCD.2012.6378682

Engineering crossbar based emerging memory technologies

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Emerging Resistive Random Access Memories (RRAM) devices are an attractive option for future memory architectures due to their low-power and high density. However, their capacity is limited by sneak paths and the sensitivity of the sense amplifiers (SA). We develop a framework to maximize the capacity of RRAM memories by modeling the interactions between memory capacity, sneak paths, device parameters, and the sense amplifier. The framework explores the design space of the memory by considering different read/write mechanisms, sneak path elimination techniques, and multi-level storage.

Original language	English (US)
Title of host publication	2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Pages	478-479
Number of pages	2
DOIs	https://doi.org/10.1109/ICCD.2012.6378682
State	Published - 2012
Event	2012 IEEE 30th International Conference on Computer Design, ICCD 2012 - Montreal, QC, Canada Duration: Sep 30 2012 → Oct 3 2012

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)	1063-6404

Other

Other	2012 IEEE 30th International Conference on Computer Design, ICCD 2012
Country/Territory	Canada
City	Montreal, QC
Period	9/30/12 → 10/3/12

Keywords

Resistive RAM
emerging memory technologies
memory design
optimization

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2012.6378682

Cite this

Engineering crossbar based emerging memory technologies. / Kannan, Sachhidh; Rajendran, Jeyavijayan; Karri, Ramesh et al.
2012 IEEE 30th International Conference on Computer Design, ICCD 2012. 2012. p. 478-479 6378682 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kannan, S, Rajendran, J, Karri, R & Sinanoglu, O 2012, Engineering crossbar based emerging memory technologies. in 2012 IEEE 30th International Conference on Computer Design, ICCD 2012., 6378682, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 478-479, 2012 IEEE 30th International Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, 9/30/12. https://doi.org/10.1109/ICCD.2012.6378682

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abstract = "Emerging Resistive Random Access Memories (RRAM) devices are an attractive option for future memory architectures due to their low-power and high density. However, their capacity is limited by sneak paths and the sensitivity of the sense amplifiers (SA). We develop a framework to maximize the capacity of RRAM memories by modeling the interactions between memory capacity, sneak paths, device parameters, and the sense amplifier. The framework explores the design space of the memory by considering different read/write mechanisms, sneak path elimination techniques, and multi-level storage.",

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language = "English (US)",

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ER -

Engineering crossbar based emerging memory technologies

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

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