Error-resilient design of branch predictors for effective yield improvement

Sobeeh Almukhaizim, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Speculative execution methods have been long employed in microprocessors in order to boost their performance. Being speculative, their implementation is self-correcting functionally, as the speculation needs always to be verified, and, if incorrect, its effect nullified. Hence, the actions of a faulty speculative component self-correct, albeit at the cost of some performance degradation. As speculation techniques are aggressively employed to enhance microprocessor's performance, however, such performance faults may result in frequent violation of their expected speculation accuracy, significantly degrading the overall performance of the system. Hence, microprocessors with defective speculative components are discarded, resulting in yield loss. In this work, we propose several error-resilient design strategies for branch predictors; a representative example of speculative processor subsystems. The proposed methods support indexing mechanisms that can effectively re-map the history information, used for predicting branches, to fault-free entries, mitigating the impact of faults in heavily-used entries. Experimental results indicate that the proposed error-resilient design methods significantly reduce the impact of performance faults, effectively improving yield.

Original languageEnglish (US)
Title of host publicationLATW 2011 - 12th IEEE Latin-American Test Workshop
StatePublished - 2011
Event12th IEEE Latin-American Test Workshop, LATW 2011 - Porto de Galinhas, Brazil
Duration: Mar 27 2011Mar 30 2011

Publication series

NameLATW 2011 - 12th IEEE Latin-American Test Workshop


Other12th IEEE Latin-American Test Workshop, LATW 2011
CityPorto de Galinhas

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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