Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL

Austin Rovinski, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Chun Zhao, Michael B. Taylor, Ronald G. Dreslinski, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva AmarnathLuis Vega

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Computer Science

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