Evaluation of the potential performance of graphene nanoribbons as on-chip interconnects

Shaloo Rakheja, Vachan Kumar, Azad Naeemi

Research output: Contribution to journalArticlepeer-review

Abstract

Interconnects are considered as one of the grandest challenges that gigascale and terascale integrations face because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. Recent studies on novel computational state variables such as electron spin have demonstrated that interconnects will continue to be an ever-growing challenge, even for post-complementary metal-oxide-semiconductor (CMOS) switches. The novel 2-D carbon-based material graphene has demonstrated remarkable electrical properties that make it a viable candidate to implement interconnects in both electrical and spintronic domains. In this paper, physical models of the electron transport parameters such as electron mean free path (MFP), diffusion coefficient, mobility, and resistance per unit length are presented for both bulk (2-D) and narrow (1-D) graphene nanoribbons (GNRs) as a function of the interconnect dimensions, edge roughness, and Fermi-energy shift. The potential of multilayer GNR (ML-GNR) as electrical interconnects is explored by taking into account the finite interlayer resistivity between the multiple layers within the ML-GNR stack. The spin-relaxation length in graphene is obtained using some theoretical estimates on the spin-orbit coupling (SOC) introduced due to ripples in graphene. It is found that, in pure graphene, the spin-relaxation length could be longer than 10 μ m; however, the presence of adatoms limits the spin-relaxation length in graphene to only 1-2 μm at room temperature. The models developed in this paper are used to benchmark graphene interconnects against their conventional copper/low- κ interconnects in both electrical and spintronic domains. The results offer important insights about the advantages and limitations of graphene interconnects and provide guidelines for technology development for this emerging interconnect technology.

Original languageEnglish (US)
Article number6520870
Pages (from-to)1740-1765
Number of pages26
JournalProceedings of the IEEE
Volume101
Issue number7
DOIs
StatePublished - 2013

Keywords

  • All-spin logic
  • edge roughness
  • graphene
  • interconnects
  • multilayer graphene
  • spin injection and transport efficiency (SITE)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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