Exploiting idle cycles for algorithm level re-computing

Kaijie Wu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Deep sub-micron VLSI circuits are susceptible to permanent and transient faults. Several techniques for concurrent error detection (CED) recovery and correction have been proposed to target permanent and transient faults. We propose a new register transfer (RT) level time redundancy based CED technique that exploits the idle cycles in the data path. Although algorithm level re-computing techniques can trade-off the detection capability of CED vs. time overhead, it results in 100 % time overhead when the strongest CED capability is achieved.. Using the idle cycles in the data path to do the re-computation can reduce this time overhead. However dependencies between operations prevent the recomputation from fully utilizing the idle cycles. Deliberately breaking some of these data dependencies can further reduce the time overhead associated with algorithm level re-computing.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages842-846
Number of pages5
DOIs
StatePublished - 2002
Event2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France
Duration: Mar 4 2002Mar 8 2002

Other

Other2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002
CountryFrance
CityParis
Period3/4/023/8/02

ASJC Scopus subject areas

  • Engineering(all)

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