Exploiting idle cycles for algorithm level re-computing

Deep sub-micron VLSI circuits are susceptible to permanent and transient faults. Several techniques for concurrent error detection (CED) recovery and correction have been proposed to target permanent and transient faults. We propose a new register transfer (RT) level time redundancy based CED technique that exploits the idle cycles in the data path. Although algorithm level re-computing techniques can trade-off the detection capability of CED vs. time overhead, it results in 100 % time overhead when the strongest CED capability is achieved.. Using the idle cycles in the data path to do the re-computation can reduce this time overhead. However dependencies between operations prevent the recomputation from fully utilizing the idle cycles. Deliberately breaking some of these data dependencies can further reduce the time overhead associated with algorithm level re-computing.