Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility

Mohammed Nabeel; Deepraj Soni; Ramesh Karri; Michail Maniatakos

doi:10.1007/978-3-031-70947-0_5

Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility

Mohammed Nabeel, Deepraj Soni, Ramesh Karri, Michail Maniatakos

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Fully Homomorphic Encryption (FHE) promises complete input privacy by allowing computation on encrypted data at the expense of high computation. FHE hardware accelerators improve performance with large and densely packed computing units, which could potentially create thermal hot spots because of high power consumption. Therefore, it is necessary to reduce the area and power consumption of the accelerator and its most critical module, i.e., the modular multiplier. In this work, we use the fact that, for FHE computation, the modulus should be of a specific form with its lower bits constrained to a decimal value of one. We examine the impact on area and power of two popular modular multiplication algorithms, Barrett and Montgomery, with different constrained widths for different modulus sizes. Our experiment results show that modular multipliers with constrained width can reduce area by 20% and power consumption by 15%-to-25%. We also propose an approximation for the number of prime moduli available with such a constrained modulus.

Original language	English (US)
Title of host publication	VLSI-SoC 2023
Subtitle of host publication	Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers
Editors	Ibrahim (Abe) M. Elfadel, Lutfi Albasha
Publisher	Springer Science and Business Media Deutschland GmbH
Pages	93-108
Number of pages	16
ISBN (Print)	9783031709463
DOIs	https://doi.org/10.1007/978-3-031-70947-0_5
State	Published - 2024
Event	31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, VLSI-SoC 2023 - Dubai, United Arab Emirates Duration: Oct 16 2023 → Oct 18 2023

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	680 IFIPAICT
ISSN (Print)	1868-4238
ISSN (Electronic)	1868-422X

Conference

Conference	31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, VLSI-SoC 2023
Country/Territory	United Arab Emirates
City	Dubai
Period	10/16/23 → 10/18/23

Keywords

ASIC Design
Barrett Reduction
Fully Homomorphic Encryption
Low-power design
Modular Multiplier
Montgomery Reduction

ASJC Scopus subject areas

Information Systems and Management

Access to Document

10.1007/978-3-031-70947-0_5

Cite this

Nabeel, M., Soni, D., Karri, R., & Maniatakos, M. (2024). Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility. In I. M. Elfadel, & L. Albasha (Eds.), VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers (pp. 93-108). (IFIP Advances in Information and Communication Technology; Vol. 680 IFIPAICT). Springer Science and Business Media Deutschland GmbH. https://doi.org/10.1007/978-3-031-70947-0_5

Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility. / Nabeel, Mohammed; Soni, Deepraj; Karri, Ramesh et al.
VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers. ed. / Ibrahim (Abe) M. Elfadel; Lutfi Albasha. Springer Science and Business Media Deutschland GmbH, 2024. p. 93-108 (IFIP Advances in Information and Communication Technology; Vol. 680 IFIPAICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nabeel, M, Soni, D, Karri, R & Maniatakos, M 2024, Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility. in IM Elfadel & L Albasha (eds), VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers. IFIP Advances in Information and Communication Technology, vol. 680 IFIPAICT, Springer Science and Business Media Deutschland GmbH, pp. 93-108, 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, VLSI-SoC 2023, Dubai, United Arab Emirates, 10/16/23. https://doi.org/10.1007/978-3-031-70947-0_5

Nabeel M, Soni D, Karri R , Maniatakos M. Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility. In Elfadel IM, Albasha L, editors, VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers. Springer Science and Business Media Deutschland GmbH. 2024. p. 93-108. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-031-70947-0_5

Nabeel, Mohammed ; Soni, Deepraj ; Karri, Ramesh et al. / Exploring Constrained-Modulus Modular Multipliers for Improved Area, Power and Flexibility. VLSI-SoC 2023: Innovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers. editor / Ibrahim (Abe) M. Elfadel ; Lutfi Albasha. Springer Science and Business Media Deutschland GmbH, 2024. pp. 93-108 (IFIP Advances in Information and Communication Technology).

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