Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

K. Cheng; A. Khakifirooz; P. Kulkarni; S. Ponoth; J. Kuss; D. Shahrjerdi; L. F. Edge; A. Kimball; S. Kanakasabapathy; K. Xiu; S. Schmitz; A. Reznicek; T. Adam; H. He; N. Loubet; S. Holmes; S. Mehta; D. Yang; A. Upham; S. C. Seo; J. L. Herman; R. Johnson; Y. Zhu; P. Jamison; B. S. Haran; Z. Zhu; L. H. Vanamurth; S. Fan; D. Horak; H. Bu; P. J. Oldiges; D. K. Sadana; P. Kozlowski; D. McHerron; J. O'Neill; B. Doris

doi:10.1109/IEDM.2009.5424422

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L. F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N. Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S. C. SeoJ. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S. Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at I_off = 300 pA/μm, V _DD = 0.9V, and L_G = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low V_T variability is achieved with A_Vt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

Original language	English (US)
Title of host publication	2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
Pages	3.2.1-3.2.4
DOIs	https://doi.org/10.1109/IEDM.2009.5424422
State	Published - 2009
Event	2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States Duration: Dec 7 2009 → Dec 9 2009

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	2009 International Electron Devices Meeting, IEDM 2009
Country/Territory	United States
City	Baltimore, MD
Period	12/7/09 → 12/9/09

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Access to Document

10.1109/IEDM.2009.5424422

Cite this

Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Kuss, J., Shahrjerdi, D., Edge, L. F., Kimball, A., Kanakasabapathy, S., Xiu, K., Schmitz, S., Reznicek, A., Adam, T., He, H., Loubet, N., Holmes, S., Mehta, S., Yang, D., Upham, A., ... Doris, B. (2009). Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest (pp. 3.2.1-3.2.4). Article 5424422 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2009.5424422

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. / Cheng, K.; Khakifirooz, A.; Kulkarni, P. et al.
2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. p. 3.2.1-3.2.4 5424422 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cheng, K, Khakifirooz, A, Kulkarni, P, Ponoth, S, Kuss, J, Shahrjerdi, D, Edge, LF, Kimball, A, Kanakasabapathy, S, Xiu, K, Schmitz, S, Reznicek, A, Adam, T, He, H, Loubet, N, Holmes, S, Mehta, S, Yang, D, Upham, A, Seo, SC, Herman, JL, Johnson, R, Zhu, Y, Jamison, P, Haran, BS, Zhu, Z, Vanamurth, LH, Fan, S, Horak, D, Bu, H, Oldiges, PJ, Sadana, DK, Kozlowski, P, McHerron, D, O'Neill, J & Doris, B 2009, Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. in 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest., 5424422, Technical Digest - International Electron Devices Meeting, IEDM, pp. 3.2.1-3.2.4, 2009 International Electron Devices Meeting, IEDM 2009, Baltimore, MD, United States, 12/7/09. https://doi.org/10.1109/IEDM.2009.5424422

Cheng K, Khakifirooz A, Kulkarni P, Ponoth S, Kuss J, Shahrjerdi D et al. Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. 2009. p. 3.2.1-3.2.4. 5424422. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2009.5424422

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title = "Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications",

abstract = "We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.",

author = "K. Cheng and A. Khakifirooz and P. Kulkarni and S. Ponoth and J. Kuss and D. Shahrjerdi and Edge, {L. F.} and A. Kimball and S. Kanakasabapathy and K. Xiu and S. Schmitz and A. Reznicek and T. Adam and H. He and N. Loubet and S. Holmes and S. Mehta and D. Yang and A. Upham and Seo, {S. C.} and Herman, {J. L.} and R. Johnson and Y. Zhu and P. Jamison and Haran, {B. S.} and Z. Zhu and Vanamurth, {L. H.} and S. Fan and D. Horak and H. Bu and Oldiges, {P. J.} and Sadana, {D. K.} and P. Kozlowski and D. McHerron and J. O'Neill and B. Doris",

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doi = "10.1109/IEDM.2009.5424422",

language = "English (US)",

isbn = "9781424456406",

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AU - Cheng, K.

AU - Khakifirooz, A.

AU - Kulkarni, P.

AU - Ponoth, S.

AU - Kuss, J.

AU - Shahrjerdi, D.

AU - Edge, L. F.

AU - Kimball, A.

AU - Kanakasabapathy, S.

AU - Xiu, K.

AU - Schmitz, S.

AU - Reznicek, A.

AU - Adam, T.

AU - He, H.

AU - Loubet, N.

AU - Holmes, S.

AU - Mehta, S.

AU - Yang, D.

AU - Upham, A.

AU - Seo, S. C.

AU - Herman, J. L.

AU - Johnson, R.

AU - Zhu, Y.

AU - Jamison, P.

AU - Haran, B. S.

AU - Zhu, Z.

AU - Vanamurth, L. H.

AU - Fan, S.

AU - Horak, D.

AU - Bu, H.

AU - Oldiges, P. J.

AU - Sadana, D. K.

AU - Kozlowski, P.

AU - McHerron, D.

AU - O'Neill, J.

AU - Doris, B.

PY - 2009

Y1 - 2009

N2 - We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

AB - We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 μA/μm, respectively, at Ioff = 300 pA/μm, V DD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV· μm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

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DO - 10.1109/IEDM.2009.5424422

M3 - Conference contribution

AN - SCOPUS:77952372091

SN - 9781424456406

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 3.2.1-3.2.4

BT - 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest

T2 - 2009 International Electron Devices Meeting, IEDM 2009

Y2 - 7 December 2009 through 9 December 2009

ER -

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

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