Extremely thin SOI for system-on-chip applications

A. Khakifirooz, K. Cheng, Q. Liu, T. Nagumo, N. Loubet, A. Reznicek, J. Kuss, J. Gimbert, R. Sreenivasan, M. Vinet, L. Grenouillet, Y. Le Tiec, R. Wacquez, Z. Ren, J. Cai, D. Shahrjerdi, P. Kulkarni, S. Ponoth, S. Luning, B. Doris

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of VT tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
StatePublished - 2012
Event34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States
Duration: Sep 9 2012Sep 12 2012

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930


Other34th Annual Custom Integrated Circuits Conference, CICC 2012
Country/TerritoryUnited States
CitySan Jose, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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