Extremely thin SOI for system-on-chip applications

A. Khakifirooz; K. Cheng; Q. Liu; T. Nagumo; N. Loubet; A. Reznicek; J. Kuss; J. Gimbert; R. Sreenivasan; M. Vinet; L. Grenouillet; Y. Le Tiec; R. Wacquez; Z. Ren; J. Cai; D. Shahrjerdi; P. Kulkarni; S. Ponoth; S. Luning; B. Doris

doi:10.1109/CICC.2012.6330618

Extremely thin SOI for system-on-chip applications

A. Khakifirooz, K. Cheng, Q. Liu, T. Nagumo, N. Loubet, A. Reznicek, J. Kuss, J. Gimbert, R. Sreenivasan, M. Vinet, L. Grenouillet, Y. Le Tiec, R. Wacquez, Z. Ren, J. Cai, D. Shahrjerdi, P. Kulkarni, S. Ponoth, S. Luning, B. Doris

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of V_T tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.

Original language	English (US)
Title of host publication	Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs	https://doi.org/10.1109/CICC.2012.6330618
State	Published - 2012
Event	34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States Duration: Sep 9 2012 → Sep 12 2012

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	34th Annual Custom Integrated Circuits Conference, CICC 2012
Country/Territory	United States
City	San Jose, CA
Period	9/9/12 → 9/12/12

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2012.6330618

Cite this

Khakifirooz, A., Cheng, K., Liu, Q., Nagumo, T., Loubet, N., Reznicek, A., Kuss, J., Gimbert, J., Sreenivasan, R., Vinet, M., Grenouillet, L., Le Tiec, Y., Wacquez, R., Ren, Z., Cai, J., Shahrjerdi, D., Kulkarni, P., Ponoth, S., Luning, S., & Doris, B. (2012). Extremely thin SOI for system-on-chip applications. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012 Article 6330618 (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2012.6330618

Khakifirooz, A, Cheng, K, Liu, Q, Nagumo, T, Loubet, N, Reznicek, A, Kuss, J, Gimbert, J, Sreenivasan, R, Vinet, M, Grenouillet, L, Le Tiec, Y, Wacquez, R, Ren, Z, Cai, J, Shahrjerdi, D, Kulkarni, P, Ponoth, S, Luning, S & Doris, B 2012, Extremely thin SOI for system-on-chip applications. in Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012., 6330618, Proceedings of the Custom Integrated Circuits Conference, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, United States, 9/9/12. https://doi.org/10.1109/CICC.2012.6330618

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abstract = "We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of VT tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.",

author = "A. Khakifirooz and K. Cheng and Q. Liu and T. Nagumo and N. Loubet and A. Reznicek and J. Kuss and J. Gimbert and R. Sreenivasan and M. Vinet and L. Grenouillet and {Le Tiec}, Y. and R. Wacquez and Z. Ren and J. Cai and D. Shahrjerdi and P. Kulkarni and S. Ponoth and S. Luning and B. Doris",

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AU - Cheng, K.

AU - Liu, Q.

AU - Nagumo, T.

AU - Loubet, N.

AU - Reznicek, A.

AU - Kuss, J.

AU - Gimbert, J.

AU - Sreenivasan, R.

AU - Vinet, M.

AU - Grenouillet, L.

AU - Le Tiec, Y.

AU - Wacquez, R.

AU - Ren, Z.

AU - Cai, J.

AU - Shahrjerdi, D.

AU - Kulkarni, P.

AU - Ponoth, S.

AU - Luning, S.

AU - Doris, B.

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AB - We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of VT tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.

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Extremely thin SOI for system-on-chip applications

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