@inproceedings{073ab7f2ea3848c09039ad3772daaa3a,
title = "Fast and energy-frugal deterministic test through test vector correlation exploitation",
abstract = "Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the scan chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also scan chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology.",
keywords = "Application software, Circuit testing, Computer science, Encoding, Flip-flops, Power dissipation, Power engineering and energy, Shift registers, Switching circuits, System-on-a-chip",
author = "O. Sinanoglu and A. Orailoglu",
note = "Funding Information: The work of the first author is supported through an IBM graduate fellowship. Publisher Copyright: {\textcopyright} 2002 IEEE.; 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002 ; Conference date: 06-11-2002 Through 08-11-2002",
year = "2002",
doi = "10.1109/DFTVS.2002.1173529",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "325--333",
booktitle = "Proceediings - 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2002",
}