Abstract
Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.
Original language | English (US) |
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Title of host publication | IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems |
Pages | 427-435 |
Number of pages | 9 |
DOIs | |
State | Published - 2001 |
Event | IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001) - San Francisco, CA, United States Duration: Oct 24 2001 → Oct 26 2001 |
Other
Other | IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001) |
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Country/Territory | United States |
City | San Francisco, CA |
Period | 10/24/01 → 10/26/01 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering