Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture

R. Karri, K. Wu, P. Mishra, Y. Kim,

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based Concurrent Error Detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for Rijndael symmetric encryption algorithm. These approaches exploit the inverse relationship that exists between Rijndael encryption and decryption at various levels and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations.

Original languageEnglish (US)
Title of host publicationIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Pages427-435
Number of pages9
DOIs
StatePublished - 2001
EventIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001) - San Francisco, CA, United States
Duration: Oct 24 2001Oct 26 2001

Other

OtherIEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001)
CountryUnited States
CitySan Francisco, CA
Period10/24/0110/26/01

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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