Fault tolerant arithmetic with applications in nanotechnology based systems

Wenjing Rao, Alex Orailogliu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Several emerging nanotechnologies have been displaying the Negative Differential Resistance (NDR) characteristic, which makes them naturally support multi-valued logic with a large number of logic states. Such multi-valued logic with a large number of logic states can support a native digit-level redundant number system and hence a native digit-level carry save arithmetic. In this paper we present a new approach to linear block code based fault-tolerant arithmetic in NDR nanotechnologies. Specifically, we show how linear block codes can be used for error checking and error correction in carry save arithmetic operations. The proposed approach significantly improves timing and fault-tolerance of arithmetic operations in the highly unreliable nanoelectronic environment. Since digit-level information redundancy via linear block codes is widely used for fault tolerant communications and storage systems, the proposed scheme also unifies the fault tolerance approaches across arithmetic, interconnection and storage subsystems.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference
Pages472-478
Number of pages7
StatePublished - 2004
EventProceedings - International Test Conference 2004 - Charlotte, NC, United States
Duration: Oct 26 2004Oct 28 2004

Other

OtherProceedings - International Test Conference 2004
CountryUnited States
CityCharlotte, NC
Period10/26/0410/28/04

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Rao, W., Orailogliu, A., & Karri, R. (2004). Fault tolerant arithmetic with applications in nanotechnology based systems. In Proceedings - International Test Conference (pp. 472-478)