TY - GEN
T1 - Fault tolerant Quantum Cellular Array (QCA) design using Triple Modular Redundancy with Shifted Operands
AU - Wei, Tongquan
AU - Wu, Kaijie
AU - Karri, Ramesh
AU - Orailoglu, Alex
PY - 2005
Y1 - 2005
N2 - Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50% area reduction and more than 100% throughput improvement when compared to a TMR implementation.
AB - Due to their extremely small feature sizes and ultra low power consumption, Quantum-dot Cellular Automata (QCA) technology is projected to be a promising nanotechnology. However, in nanotechnologies, manufacture time defect levels and operational time fault rates are expected to be quite high. Straightforward Triple Modular Redundancy (TMR) based fault tolerance is inappropriate for QCA nanotechnology since wire delays dominate the logic delays and faults in wires dominate the faults in a QCA based design. Furthermore, long wires are necessary in TMR based designs. In this paper we show that fault-tolerance can be obtained by using TMR with Shifted Operands (TMRSO). TMRSO uses shorter wires of QCA cells and exploits the self-latching property of clocked QCA arrays to provide the same level of fault tolerance capability as straightforward TMR while being significantly faster and smaller. This technique can be applied to a variety of operations; we have validated TMRSO on adders. Implementation results obtained using QCADesigner [6] show that an 8-bit adder using TMRSO has more than 50% area reduction and more than 100% throughput improvement when compared to a TMR implementation.
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U2 - 10.1145/1120725.1120938
DO - 10.1145/1120725.1120938
M3 - Conference contribution
AN - SCOPUS:84861448153
SN - 0780387368
SN - 9780780387362
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 1192
EP - 1195
BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Y2 - 18 January 2005 through 21 January 2005
ER -