Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

Jeff Jun Zhang, Kanad Basu, Siddharth Garg

Research output: Contribution to journalArticle

Abstract

Editor's note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. - Yiran Chen, Duke University.

Original languageEnglish (US)
Article number8709714
Pages (from-to)44-53
Number of pages10
JournalIEEE Design and Test
Volume36
Issue number5
DOIs
StatePublished - Oct 2019

Keywords

  • Deep Neural Networks
  • Fault Toerance
  • Reliability
  • Systolic Arrays
  • Testing

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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