Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

Jeff Jun Zhang; Kanad Basu; Siddharth Garg

doi:10.1109/MDAT.2019.2915656

Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

Jeff Jun Zhang, Kanad Basu, Siddharth Garg

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

Editor's note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. - Yiran Chen, Duke University.

Original language	English (US)
Article number	8709714
Pages (from-to)	44-53
Number of pages	10
Journal	IEEE Design and Test
Volume	36
Issue number	5
DOIs	https://doi.org/10.1109/MDAT.2019.2915656
State	Published - Oct 2019

Keywords

Deep Neural Networks
Fault Toerance
Reliability
Systolic Arrays
Testing

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MDAT.2019.2915656

Cite this

@article{e5b08abab97c43a1bad398c0e1f026eb,

title = "Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution",

abstract = "Editor's note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. - Yiran Chen, Duke University.",

keywords = "Deep Neural Networks, Fault Toerance, Reliability, Systolic Arrays, Testing",

author = "Zhang, {Jeff Jun} and Kanad Basu and Siddharth Garg",

note = "Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2019",

month = oct,

doi = "10.1109/MDAT.2019.2915656",

language = "English (US)",

volume = "36",

pages = "44--53",

journal = "IEEE Design and Test",

issn = "2168-2356",

publisher = "IEEE Computer Society",

number = "5",

}

TY - JOUR

T1 - Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

AU - Zhang, Jeff Jun

AU - Basu, Kanad

AU - Garg, Siddharth

PY - 2019/10

Y1 - 2019/10

N2 - Editor's note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. - Yiran Chen, Duke University.

AB - Editor's note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. - Yiran Chen, Duke University.

KW - Deep Neural Networks

KW - Fault Toerance

KW - Reliability

KW - Systolic Arrays

KW - Testing

UR - http://www.scopus.com/inward/record.url?scp=85065673469&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065673469&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2019.2915656

DO - 10.1109/MDAT.2019.2915656

M3 - Article

AN - SCOPUS:85065673469

SN - 2168-2356

VL - 36

SP - 44

EP - 53

JO - IEEE Design and Test

JF - IEEE Design and Test

IS - 5

M1 - 8709714

ER -

Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this