Feasibility study of dynamic trusted platform module

Arun K. Kanuparthi; Mohamed Zahran; Ramesh Karri

doi:10.1109/ICCD.2010.5647705

Feasibility study of dynamic trusted platform module

Arun K. Kanuparthi, Mohamed Zahran, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A Trusted Platform Module (TPM) authenticates general purpose computing platforms. This is done by taking platform integrity measurement and comparing it with a precomputed value at boot-time. Existing TPM architectures do not support run-time integrity checking of a program on the platform. Attackers can modify the program after it has been verified at the Time Of Check (TOC) and before its Time Of Use (TOU). In this paper we study the feasibility of integrating a dynamic on-chip TPM (DTPM) into the core processor pipeline to protect against TOCTOU attacks. We explore the challenges involved in designing DTPM and describe techniques to improve its performance. The proposed DTPM has 2.5% area overhead and 18% performance impact when compared to a single processor core without DTPM.

Original language	English (US)
Title of host publication	2010 IEEE International Conference on Computer Design, ICCD 2010
Pages	350-355
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2010.5647705
State	Published - 2010
Event	28th IEEE International Conference on Computer Design, ICCD 2010 - Amsterdam, Netherlands Duration: Oct 3 2010 → Oct 6 2010

Publication series

Name	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)	1063-6404

Other

Other	28th IEEE International Conference on Computer Design, ICCD 2010
Country/Territory	Netherlands
City	Amsterdam
Period	10/3/10 → 10/6/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2010.5647705

Cite this

Feasibility study of dynamic trusted platform module. / Kanuparthi, Arun K.; Zahran, Mohamed; Karri, Ramesh.
2010 IEEE International Conference on Computer Design, ICCD 2010. 2010. p. 350-355 5647705 (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kanuparthi, AK, Zahran, M & Karri, R 2010, Feasibility study of dynamic trusted platform module. in 2010 IEEE International Conference on Computer Design, ICCD 2010., 5647705, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 350-355, 28th IEEE International Conference on Computer Design, ICCD 2010, Amsterdam, Netherlands, 10/3/10. https://doi.org/10.1109/ICCD.2010.5647705

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title = "Feasibility study of dynamic trusted platform module",

abstract = "A Trusted Platform Module (TPM) authenticates general purpose computing platforms. This is done by taking platform integrity measurement and comparing it with a precomputed value at boot-time. Existing TPM architectures do not support run-time integrity checking of a program on the platform. Attackers can modify the program after it has been verified at the Time Of Check (TOC) and before its Time Of Use (TOU). In this paper we study the feasibility of integrating a dynamic on-chip TPM (DTPM) into the core processor pipeline to protect against TOCTOU attacks. We explore the challenges involved in designing DTPM and describe techniques to improve its performance. The proposed DTPM has 2.5% area overhead and 18% performance impact when compared to a single processor core without DTPM.",

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note = "28th IEEE International Conference on Computer Design, ICCD 2010 ; Conference date: 03-10-2010 Through 06-10-2010",

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AB - A Trusted Platform Module (TPM) authenticates general purpose computing platforms. This is done by taking platform integrity measurement and comparing it with a precomputed value at boot-time. Existing TPM architectures do not support run-time integrity checking of a program on the platform. Attackers can modify the program after it has been verified at the Time Of Check (TOC) and before its Time Of Use (TOU). In this paper we study the feasibility of integrating a dynamic on-chip TPM (DTPM) into the core processor pipeline to protect against TOCTOU attacks. We explore the challenges involved in designing DTPM and describe techniques to improve its performance. The proposed DTPM has 2.5% area overhead and 18% performance impact when compared to a single processor core without DTPM.

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Feasibility study of dynamic trusted platform module

Abstract

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Other

ASJC Scopus subject areas

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