Fine-grained voltage boosting for improving yield in near-threshold many-core processors

Joonho Kong, Arslan Munir, Farinaz Koushanfar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Process variation is a major impediment in optimizing yield, energy, and performance in near-threshold many-core processors. In this paper, we present a comprehensive analysis on yield losses in near-threshold many-core processors. Based on our analysis, we propose energyefficient yield improvement techniques for near-threshold many-core processors: SRAM cell arrays and Wordline driver voltage Boosting (SWBoost) and Cache voltage Boosting (CBoost). Results reveal that SWBoost and CBoost improve a chip yield by up to 66% and 83%, respectively. Furthermore, runtime energy overheads of SWBoost and CBoost are only 0.46% and 0.54%, respectively, which are much lower than conventional voltage boosting techniques.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages225-228
Number of pages4
ISBN (Electronic)9781450334747
DOIs
StatePublished - May 20 2015
Event25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States
Duration: May 20 2015May 22 2015

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Volume20-22-May-2015

Conference

Conference25th Great Lakes Symposium on VLSI, GLSVLSI 2015
Country/TerritoryUnited States
CityPittsburgh
Period5/20/155/22/15

Keywords

  • Near-threshold computing
  • Process variations
  • Voltage boosting
  • Yield

ASJC Scopus subject areas

  • General Engineering

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