TY - GEN
T1 - Flow control in a multi-plane multi-stage buffered packet switch
AU - Chao, H. Jonathan
AU - Park, Jinsoo
PY - 2007
Y1 - 2007
N2 - A large-capacity, multi-plane, multi-stage buffered packet switch, called the TrueWay switch [1], was previously proposed by us. It can achieve hundreds of terabits/sec capacity. A small-scale TrueWay switch was prototyped to demonstrate the concept and feasibility. Three different load balancing schemes were investigated to achieve high throughput and low average delay with a moderate speedup. In this paper, we focus on the study of one of the load balancing schemes, window-based re-sequencing scheme, without a speedup. It is the most promising one among the three in terms of performance. Buffered switch modules are used in different stages to eliminate the need of centralized scheduling. However, packet out-of-subsequence is inventible as packets are distributed to different paths that have various queuing delays. By applying flow control between the input and output ports and limiting the re-sequencing window size (similar to TCP/IP flow control), we are able to keep the implementation cost to an acceptable level while still providing high throughput. Link-level flow control between the switch stages is required to prevent the downstream queues from being overflowed. The interaction between link flow control at switch stages and end-to-end flow control at switch ports is an interesting problem. We show by simulations that the TrueWay switch can be engineered to achieve high throughput without an internal speedup even under bursty non-uniform traffic distributions.
AB - A large-capacity, multi-plane, multi-stage buffered packet switch, called the TrueWay switch [1], was previously proposed by us. It can achieve hundreds of terabits/sec capacity. A small-scale TrueWay switch was prototyped to demonstrate the concept and feasibility. Three different load balancing schemes were investigated to achieve high throughput and low average delay with a moderate speedup. In this paper, we focus on the study of one of the load balancing schemes, window-based re-sequencing scheme, without a speedup. It is the most promising one among the three in terms of performance. Buffered switch modules are used in different stages to eliminate the need of centralized scheduling. However, packet out-of-subsequence is inventible as packets are distributed to different paths that have various queuing delays. By applying flow control between the input and output ports and limiting the re-sequencing window size (similar to TCP/IP flow control), we are able to keep the implementation cost to an acceptable level while still providing high throughput. Link-level flow control between the switch stages is required to prevent the downstream queues from being overflowed. The interaction between link flow control at switch stages and end-to-end flow control at switch ports is an interesting problem. We show by simulations that the TrueWay switch can be engineered to achieve high throughput without an internal speedup even under bursty non-uniform traffic distributions.
KW - Clos network
KW - Multi-plane switch
KW - Packet switch
UR - http://www.scopus.com/inward/record.url?scp=47649111338&partnerID=8YFLogxK
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U2 - 10.1109/HPSR.2007.4281256
DO - 10.1109/HPSR.2007.4281256
M3 - Conference contribution
AN - SCOPUS:47649111338
SN - 1424412064
SN - 9781424412068
T3 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
SP - 18
EP - 23
BT - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
T2 - 2007 IEEE Workshop on High Performance Switching and Routing, HPSR
Y2 - 30 May 2007 through 1 June 2007
ER -