Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Globalization of the system-on-chip (SoC) design flow has created opportunities for rogue intellectual property (IP) vendors to insert malicious circuits (a.k.a. hardware Trojans) into their IPs. We propose to formally verify third party IPs (3PIPs) for unauthorized information leakage. We validate our technique using Trojan benchmarks from the Trust-Hub.

Original languageEnglish (US)
Title of host publicationProceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems
PublisherIEEE Computer Society
Pages547-552
Number of pages6
ISBN (Electronic)9781467387002
DOIs
StatePublished - Mar 16 2016
Event29th International Conference on VLSI Design, VLSID 2016 - Kolkata, India
Duration: Jan 4 2016Jan 8 2016

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2016-March
ISSN (Print)1063-9667

Other

Other29th International Conference on VLSI Design, VLSID 2016
CountryIndia
CityKolkata
Period1/4/161/8/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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