Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

Jeyavijayan Rajendran; Arunshankar Muruga Dhandayuthapany; Vivekananda Vedula; Ramesh Karri

doi:10.1109/VLSID.2016.143

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Globalization of the system-on-chip (SoC) design flow has created opportunities for rogue intellectual property (IP) vendors to insert malicious circuits (a.k.a. hardware Trojans) into their IPs. We propose to formally verify third party IPs (3PIPs) for unauthorized information leakage. We validate our technique using Trojan benchmarks from the Trust-Hub.

Original language	English (US)
Title of host publication	Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems
Publisher	IEEE Computer Society
Pages	547-552
Number of pages	6
ISBN (Electronic)	9781467387002
DOIs	https://doi.org/10.1109/VLSID.2016.143
State	Published - Mar 16 2016
Event	29th International Conference on VLSI Design, VLSID 2016 - Kolkata, India Duration: Jan 4 2016 → Jan 8 2016

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
Volume	2016-March
ISSN (Print)	1063-9667

Other

Other	29th International Conference on VLSI Design, VLSID 2016
Country/Territory	India
City	Kolkata
Period	1/4/16 → 1/8/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSID.2016.143

Cite this

Rajendran, J., Dhandayuthapany, A. M., Vedula, V., & Karri, R. (2016). Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. In Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems (pp. 547-552). Article 7435011 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2016-March). IEEE Computer Society. https://doi.org/10.1109/VLSID.2016.143

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. / Rajendran, Jeyavijayan; Dhandayuthapany, Arunshankar Muruga; Vedula, Vivekananda et al.
Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. IEEE Computer Society, 2016. p. 547-552 7435011 (Proceedings of the IEEE International Conference on VLSI Design; Vol. 2016-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rajendran, J, Dhandayuthapany, AM, Vedula, V & Karri, R 2016, Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. in Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems., 7435011, Proceedings of the IEEE International Conference on VLSI Design, vol. 2016-March, IEEE Computer Society, pp. 547-552, 29th International Conference on VLSI Design, VLSID 2016, Kolkata, India, 1/4/16. https://doi.org/10.1109/VLSID.2016.143

Rajendran J, Dhandayuthapany AM, Vedula V, Karri R. Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. In Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. IEEE Computer Society. 2016. p. 547-552. 7435011. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSID.2016.143

Rajendran, Jeyavijayan ; Dhandayuthapany, Arunshankar Muruga ; Vedula, Vivekananda et al. / Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. Proceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems. IEEE Computer Society, 2016. pp. 547-552 (Proceedings of the IEEE International Conference on VLSI Design).

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Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

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