FPGA controlled WDM buffer memory

L. Wu; H. J. Chao; X. J. Zhao; Y. Zhao; Y. Chai; J. P. Zhang; F. S. Choa

doi:10.1109/cleo.2000.907089

FPGA controlled WDM buffer memory

L. Wu, H. J. Chao, X. J. Zhao, Y. Zhao, Y. Chai, J. P. Zhang, F. S. Choa

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

An overview is given on a recent work on a WDM loop memory controlled by an FPGA (Field Programmable Gate Array) chip. The WDM loop memory is designed for use in a 4 × 4 shared-memory multicast switch.

Original language	English (US)
Pages	340-341
Number of pages	2
DOIs	https://doi.org/10.1109/cleo.2000.907089
State	Published - 2000
Event	Conference on Lasers and Electro-Optics (CLEO 2000) - San Francisco, CA, USA Duration: May 7 2000 → May 12 2000

Other

Other	Conference on Lasers and Electro-Optics (CLEO 2000)
City	San Francisco, CA, USA
Period	5/7/00 → 5/12/00

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/cleo.2000.907089

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@conference{81afeb5cf59349c88716ea93efa52657,

title = "FPGA controlled WDM buffer memory",

abstract = "An overview is given on a recent work on a WDM loop memory controlled by an FPGA (Field Programmable Gate Array) chip. The WDM loop memory is designed for use in a 4 × 4 shared-memory multicast switch.",

author = "L. Wu and Chao, {H. J.} and Zhao, {X. J.} and Y. Zhao and Y. Chai and Zhang, {J. P.} and Choa, {F. S.}",

year = "2000",

doi = "10.1109/cleo.2000.907089",

language = "English (US)",

pages = "340--341",

note = "Conference on Lasers and Electro-Optics (CLEO 2000) ; Conference date: 07-05-2000 Through 12-05-2000",

}

TY - CONF

T1 - FPGA controlled WDM buffer memory

AU - Wu, L.

AU - Chao, H. J.

AU - Zhao, X. J.

AU - Zhao, Y.

AU - Chai, Y.

AU - Zhang, J. P.

AU - Choa, F. S.

PY - 2000

Y1 - 2000

N2 - An overview is given on a recent work on a WDM loop memory controlled by an FPGA (Field Programmable Gate Array) chip. The WDM loop memory is designed for use in a 4 × 4 shared-memory multicast switch.

AB - An overview is given on a recent work on a WDM loop memory controlled by an FPGA (Field Programmable Gate Array) chip. The WDM loop memory is designed for use in a 4 × 4 shared-memory multicast switch.

UR - http://www.scopus.com/inward/record.url?scp=0034539569&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034539569&partnerID=8YFLogxK

U2 - 10.1109/cleo.2000.907089

DO - 10.1109/cleo.2000.907089

M3 - Paper

AN - SCOPUS:0034539569

SP - 340

EP - 341

T2 - Conference on Lasers and Electro-Optics (CLEO 2000)

Y2 - 7 May 2000 through 12 May 2000

ER -

FPGA controlled WDM buffer memory

Abstract

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ASJC Scopus subject areas

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