TY - GEN
T1 - FPGA-Patch
T2 - 2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023
AU - Ahmadi, Mahya Morid
AU - Alrahis, Lilas
AU - Sinanoglu, Ozgur
AU - Shafique, Muhammad
N1 - Funding Information:
VI. ACKNOWLEDGEMENT This work is supported by the Doctoral College Resilient Embedded Systems, which is run jointly by the TU Wien’s Faculty of Informatics and the UAS Technikum Wien and is part of the Moore4Medical project funded by the ECSEL Joint Undertaking under grant number H2020-ECSEL-2019-IA-876190. It is also jointly supported by the Center for Cyber Security (CCS) at New York University Abu Dhabi.
Funding Information:
This work is supported by the Doctoral College Resilient Embedded Systems, which is run jointly by the TU Wien's Faculty of Informatics and the UAS Technikum Wien and is part of the Moore4Medical project funded by the ECSEL Joint Undertaking under grant number H2020-ECSEL-2019- IA-876190. It is also jointly supported by the Center for Cyber Security (CCS) at New York University Abu Dhabi.
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - We propose FPGA-Patch, the first-of-its-kind defense that leverages automated program repair concepts to thwart power side-channel attacks on cloud FPGAs. FPGA-Patch generates isofunctional variants of the target hardware by injecting faults and finding transformations that eliminate failure. The obtained variants display different hardware characteristics, ensuring a maximal diversity in power traces once dynamically swapped at run-time. Yet, FPGA-Patch forces the variants to have enough similarity, enabling bitstream compression and minimizing dynamic exchange costs. Considering AES running on AMD/Xilinx FPGA, FPGA-Patch increases the attacker's effort by three orders of magnitude, while preserving the performance of AES and a minimal area overhead of 14.2%.
AB - We propose FPGA-Patch, the first-of-its-kind defense that leverages automated program repair concepts to thwart power side-channel attacks on cloud FPGAs. FPGA-Patch generates isofunctional variants of the target hardware by injecting faults and finding transformations that eliminate failure. The obtained variants display different hardware characteristics, ensuring a maximal diversity in power traces once dynamically swapped at run-time. Yet, FPGA-Patch forces the variants to have enough similarity, enabling bitstream compression and minimizing dynamic exchange costs. Considering AES running on AMD/Xilinx FPGA, FPGA-Patch increases the attacker's effort by three orders of magnitude, while preserving the performance of AES and a minimal area overhead of 14.2%.
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U2 - 10.1109/ISLPED58423.2023.10244526
DO - 10.1109/ISLPED58423.2023.10244526
M3 - Conference contribution
AN - SCOPUS:85171622171
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - 2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 7 August 2023 through 8 August 2023
ER -