Framework for fault-tolerant microarchitecture synthesis

The trend towards VLSI implementation of crucial tasks in life-critical, mission-critical, and safety-critical applications (such as automobile/process control systems and medical instrumentation) is stimulating the need for on-chip fault-tolerance. The growing demand for quality and fault-tolerance (in addition to speed and reduced area), coupled with the inherent unreliability attendant upon VLSI, has elevated the design of fault-tolerant VLSI systems into a research problem of practical relevance. In this paper, we present a framework that subsumes algorithms for synthesizing self-recovering, fault-secure, and reliable microarchitectures.