This paper describes Flexible Set Balancing (FSB), a practical strategy for providing high-performance caching. Our work is motivated by a large asymmetry in the usage of cache sets. FSB extends the lifetime of cache lines via retaining some fraction of the working set at underutilized sets to satisfy far-flung reuses. FSB promotes a very flexible sharing among cache sets, referred to as many-from-many sharing, providing significant reduction in interference misses. Simulation results using a full-system simulator that models a 16-way tiled chip multiprocessor platform demonstrate that FSB achieves an average miss rate reduction of 36.6% on multithreading and multiprogramming benchmarks from SPEC2006, PARSEC, and SPLASH-2 suites. This translates into an average execution-time improvement of 13%. Furthermore, evaluations showed the outperformance of FSB over some recent proposals including DSBC  and V-WAY .
|Original language||English (US)|
|Title of host publication||Multicore Computing|
|Subtitle of host publication||Algorithms, Architectures, and Applications|
|Number of pages||28|
|State||Published - Jan 1 2013|
ASJC Scopus subject areas
- Computer Science(all)