Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Ali Khakifirooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam Shahidi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1-5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.

Original languageEnglish (US)
Title of host publication2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages152-153
Number of pages2
DOIs
StatePublished - 2010
Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
Duration: Feb 7 2010Feb 11 2010

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume53
ISSN (Print)0193-6530

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
CountryUnited States
CitySan Francisco, CA
Period2/7/102/11/10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Khakifirooz, A., Cheng, K., Jagannathan, B., Kulkarni, P., Sleight, J. W., Shahrjerdi, D., Chang, J. B., Lee, S., Li, J., Bu, H., Gauthier, R., Doris, B., & Shahidi, G. (2010). Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 152-153). [5434014] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5434014