Generalized priority queue manager design for ATM switches

Our concern is the problem of efficiently supporting multiple QOS requirements in ATM networks. A queue manager in ATM network nodes schedules cells' transmission based on their urgencies at the decision moment, while it controls buffer access based on the cells' loss priorities. In this paper, we propose a generalized priority queue manager (GPQM) which supports multiple QOS requirements in class level while also guaranteeing fairness in connection level. It adopts the Self-Clocked Fair Queueing (SCFQ) algorithm to achieve fairness and the Earliest-Due-Date (EDD) scheme to meet various delay requirements. It supports delay requirements management in class level as well as fair scheduling in connection level. For buffer management, it adopts Self-Calibrating Pushout (SCP) for class level control followed by connection level head-of-line cell discarding. The SCP buffer management scheme allows the buffer to be completely shared by all service classes. Moreover, it keeps almost identical cell loss rate among connections in the same loss priority. We present a practical architecture to implement GPQM, facilitated by a new VLSI chip (called Generalized Sequencer chip), an enhanced version of the existing Sequencer chip.