TY - JOUR
T1 - Golden-Free Robust Age Estimation to Triage Recycled ICs
AU - Surabhi, Virinchi Roy
AU - Krishnamurthy, Prashanth
AU - Amrouch, Hussam
AU - Henkel, Jorg
AU - Karri, Ramesh
AU - Khorrami, Farshad
N1 - Funding Information:
This work was supported in part by the Office of Naval Research under Grant N00014-21-1-2390 and Grant N00014-22-1-2314
Publisher Copyright:
© 2023 IEEE.
PY - 2023/9/1
Y1 - 2023/9/1
N2 - Nondestructive golden-free detection of recycled/counterfeit integrated circuits (ICs) is the focus of this article. This is achieved by estimating the functional/operational age of the IC. The age estimation method is based on exploiting short-term aging effects in advanced transistor technologies to induce bit errors at the IC's output. Gate-level simulations are used to capture the impact of workload on short-term aging. In advanced technology nodes, including bulk CMOS at 45 nm or below and FinFET, combining transistor aging with ultrafast voltage scaling magnifies the effects of aging-induced degradation at high voltage when voltage scales to a lower level, causing short-term aging-based timing violations. These timing violations create bit errors at IC outputs. We employ the bit error patterns to build a machine learning (ML)-based nonlinear regression model to estimate the IC's age. Our study confirms that short-term aging-induced output bit error patterns can be used to estimate long-term age of an IC. If the IC's age is beyond a predefined threshold, it can be marked as recycled. Although this article considers the FinFET technology, the method applies to bulk CMOS advanced nodes at 45 nm or below. We model IC-to-IC variations taking into account the voltage scaling. We demonstrate the approach on two cryptographic ICs and the method accurately estimates the long-term age of an IC, facilitating recycled IC detection.
AB - Nondestructive golden-free detection of recycled/counterfeit integrated circuits (ICs) is the focus of this article. This is achieved by estimating the functional/operational age of the IC. The age estimation method is based on exploiting short-term aging effects in advanced transistor technologies to induce bit errors at the IC's output. Gate-level simulations are used to capture the impact of workload on short-term aging. In advanced technology nodes, including bulk CMOS at 45 nm or below and FinFET, combining transistor aging with ultrafast voltage scaling magnifies the effects of aging-induced degradation at high voltage when voltage scales to a lower level, causing short-term aging-based timing violations. These timing violations create bit errors at IC outputs. We employ the bit error patterns to build a machine learning (ML)-based nonlinear regression model to estimate the IC's age. Our study confirms that short-term aging-induced output bit error patterns can be used to estimate long-term age of an IC. If the IC's age is beyond a predefined threshold, it can be marked as recycled. Although this article considers the FinFET technology, the method applies to bulk CMOS advanced nodes at 45 nm or below. We model IC-to-IC variations taking into account the voltage scaling. We demonstrate the approach on two cryptographic ICs and the method accurately estimates the long-term age of an IC, facilitating recycled IC detection.
KW - FinFET technology
KW - IC age determination
KW - machine learning (ML)
KW - recycled integrated circuit (IC) detection
KW - short-term aging
UR - http://www.scopus.com/inward/record.url?scp=85147312034&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85147312034&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2023.3238291
DO - 10.1109/TCAD.2023.3238291
M3 - Article
AN - SCOPUS:85147312034
SN - 0278-0070
VL - 42
SP - 2839
EP - 2851
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
ER -