TY - GEN
T1 - Graph Neural Networks
T2 - 28th Asia and South Pacific Design Automation Conference, ASP-DAC 2023
AU - Alrahis, Lilas
AU - Knechtel, Johann
AU - Sinanoglu, Ozgur
N1 - Publisher Copyright:
© 2023 Copyright held by the owner/author(s).
PY - 2023/1/16
Y1 - 2023/1/16
N2 - Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. Given this trajectory, there is a timely need to review and discuss some powerful and versatile GNN approaches for advancing IC design. In this paper, we propose a generic pipeline for tailoring GNN models toward solving challenging problems for IC design. We outline promising options for each pipeline element, and we discuss selected and promising works, like leveraging GNNs to break SOTA logic obfuscation. Our comprehensive overview of GNNs frameworks covers (i) electronic design automation (EDA) and IC design in general, (ii) design of reliable ICs, and (iii) design as well as analysis of secure ICs. We provide our overview and related resources also in the GNN4IC hub at https://github.com/DfX-NYUAD/GNN4IC. Finally, we discuss interesting open problems for future research.
AB - Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. Given this trajectory, there is a timely need to review and discuss some powerful and versatile GNN approaches for advancing IC design. In this paper, we propose a generic pipeline for tailoring GNN models toward solving challenging problems for IC design. We outline promising options for each pipeline element, and we discuss selected and promising works, like leveraging GNNs to break SOTA logic obfuscation. Our comprehensive overview of GNNs frameworks covers (i) electronic design automation (EDA) and IC design in general, (ii) design of reliable ICs, and (iii) design as well as analysis of secure ICs. We provide our overview and related resources also in the GNN4IC hub at https://github.com/DfX-NYUAD/GNN4IC. Finally, we discuss interesting open problems for future research.
UR - http://www.scopus.com/inward/record.url?scp=85148485729&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85148485729&partnerID=8YFLogxK
U2 - 10.1145/3566097.3568345
DO - 10.1145/3566097.3568345
M3 - Conference contribution
AN - SCOPUS:85148485729
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 83
EP - 90
BT - ASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 16 January 2023 through 19 January 2023
ER -