HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors

Yatish Turakhia, Bharathwaj Raghunathan, Siddharth Garg, Diana Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this paper, we propose an efficient iterative optimization based approach for architectural synthesis of dark silicon heterogeneous chip multi-processors (CMPs). The goal is to determine the optimal number of cores of each type to provision the CMP with, such that the area and power budgets are met and the application performance is maximized. We consider general-purpose multi-threaded applications with a varying degree of parallelism (DOP) that can be set at run-time, and propose an accurate analytical model to predict the execution time of such applications on heterogeneous CMPs. Our experimental results illustrate that the synthesized heterogeneous dark silicon CMPs provide between 19% to 60% performance improvements over conventional homogeneous designs for variable and fixed DOP scenarios, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the 50th Annual Design Automation Conference, DAC 2013
Number of pages6
StatePublished - 2013
Event50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
Duration: May 29 2013Jun 7 2013

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other50th Annual Design Automation Conference, DAC 2013
Country/TerritoryUnited States
CityAustin, TX

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation


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