TY - GEN
T1 - Hardware accelerated convolutional neural networks for synthetic vision systems
AU - Farabet, Clément
AU - Martini, Berin
AU - Akselrod, Polina
AU - Talay, Selçuk
AU - LeCun, Yann
AU - Culurciello, Eugenio
PY - 2010
Y1 - 2010
N2 - In this paper we present a scalable hardware architecture to implement large-scale convolutional neural networks and state-of-the-art multi-layered artificial vision systems. This system is fully digital and is a modular vision engine with the goal of performing real-time detection, recognition and segmentation of mega-pixel images. We present a performance comparison between a software, FPGA and ASIC implementation that shows a speed up in custom hardware implementations.
AB - In this paper we present a scalable hardware architecture to implement large-scale convolutional neural networks and state-of-the-art multi-layered artificial vision systems. This system is fully digital and is a modular vision engine with the goal of performing real-time detection, recognition and segmentation of mega-pixel images. We present a performance comparison between a software, FPGA and ASIC implementation that shows a speed up in custom hardware implementations.
UR - http://www.scopus.com/inward/record.url?scp=77956000290&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956000290&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537908
DO - 10.1109/ISCAS.2010.5537908
M3 - Conference contribution
AN - SCOPUS:77956000290
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 257
EP - 260
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -